| 摘要 |
A gate addressing system of a logic simulation machine for performing translation from data of a circuit design data base to circuit data for the logic simulation machine, a) means for numbering each input terminal of a circuit and each gate of said circuit without using numbers determined based on the number of fanout gates to which an output signal of an input terminal or a gate is applied between numbers of one input terminal and another input terminal, one input terminal and one gate, one gate and another gate or one gate and one input terminal; and b) means for starting, in a table representing connection relationships among input terminals and gates and among gates, a list of numbers of fanout gates of each input terminal or each gate at an address as the number assigned to said input terminal and gate. <IMAGE> |
