Clock signal multiplier circuit for a clock signal generator circuit

摘要

The present invention provides a multiplying circuit comprising : an oscillation control circuit for alternately activating first and second oscillation control signals for every clocks of an input clock signal ; a first pulse signal generator circuit connected to the oscillation control circuit for receiving the first oscillation control signal so that the first pulse signal generator circuit generates a first multiplied clock signal having a higher frequency than the input clock signal only when the first oscillation control signal is in an activated state ; a second pulse signal generator circuit connected to the oscillation control circuit for receiving the second oscillation control signal so that the second pulse signal generator circuit generates a second multiplied clock signal having a higher frequency than the input clock signal only when the second oscillation control signal is in an activated state ; and an output circuit connected to the first and second pulse signal generator circuits for receiving the first and second multiplied clock signals and selectively outputting the first and second multiplied clock signals as an multiplied output clock signal. <IMAGE>