发明名称
摘要 <p>PURPOSE:To efficiently execute data erasing processing and to shorten time required for erasing processing by writing one digital data in each of plural semiconductor chips when the number of digital data to be written is less than the number of semiconductor memory chips. CONSTITUTION:Data A are written in the blocks 13a to 13c of block numbers (1) to (3) (physical addresses), data B are written in the blocks 14a to 14c of block numbers (5) to (7) (physical addresses) and data C are written in the blocks 15a to 15c of block numbers (9) to (11) (physical addresses). Since chip erasing can be executed by distributing and recording respective data A to C in respective EEPROM chips 13 to 15 even in the case of erasing any data A, B or C, data erasing processing can be efficiently executed, time required for erasing processing can be shortened and rapid data rewriting can be executed.</p>
申请公布号 JP3406622(B2) 申请公布日期 2003.05.12
申请号 JP19920292567 申请日期 1992.10.30
申请人 发明人
分类号 G06F12/06;G06F12/00;G06F12/02;G06K19/07;G11C16/02;G11C16/06;G11C17/00;(IPC1-7):G06F12/02 主分类号 G06F12/06
代理机构 代理人
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