发明名称 Impurity co-implantation to improve transistor performance
摘要 A pMOS transistor having reduced diffusion from source/drain regions and a method of forming the same are provided. The pMOS transistor includes a source/drain region doped with a p-type impurity and a diffusion-retarding material in a semiconductor substrate. The pMOS transistor further includes a gate dielectric over a channel region in the semiconductor substrate, a gate electrode over the gate dielectric, and a lightly doped source/drain (LDD) region substantially aligned with an edge of the gate electrode. The diffusion-retarding material preferably includes carbon, fluorine, nitrogen, and combinations thereof.
申请公布号 US2006284249(A1) 申请公布日期 2006.12.21
申请号 US20050157515 申请日期 2005.06.21
申请人 CHEN CHIEN-HAO;NIEH CHUN-FENG;LEE TZE-LIANG;CHEN SHIH-CHANG 发明人 CHEN CHIEN-HAO;NIEH CHUN-FENG;LEE TZE-LIANG;CHEN SHIH-CHANG
分类号 H01L21/8238 主分类号 H01L21/8238
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