High speed circuit assembly with integral terminal and mating bias loading electrical connector assembly

摘要

A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.

主权项

1. A circuit assembly comprising:
an array of integral terminals plated on a first circuit member comprising an electro-lessly plated shell with an electro-plated core. the integral terminals including at least one undercut; a printed circuit board with a plurality of recesses configured to receive the integral terminals; and a plurality of contact members electrically coupled with circuitry on a major surface of the printed circuit board and extending into a recesses generally parallel to the major surface; wherein insertion of the integral terminals on the first circuit member into the recesses on the PCB is a zero or low insertion force process, such that shifting the first circuit member relative to the printed circuit board generally parallel to the major surface electrically couples the contact members with the undercuts on the integral terminals.