发明名称
摘要 A digital signal processor in which the control device transmits to and writes into the buffer memory the data necessary for multiplication or for generating addresses in the external memory, and then the data in the buffer memory is written into the internal memory during a single sampling period. This processing device contains an address comparator that compares the address set by the control device in the internal memory into which the data in the buffer memory is written, with the address in the internal memory controlled by the program, and then that produces control signals to write the data read from the buffer memory into the internal memory. The data read from the buffer memory is written into the internal memory, and is also used for multiplication or for generating addresses in the external memory.
申请公布号 JP2680483(B2) 申请公布日期 1997.11.19
申请号 JP19910100799 申请日期 1991.05.02
申请人 发明人
分类号 G10K15/12;G06F17/10;G10H1/12 主分类号 G10K15/12
代理机构 代理人
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