| 摘要 |
PROBLEM TO BE SOLVED: To obtain a clock generation circuit generating a clock without causing any jitter. SOLUTION: A counter 1 presets reference time information received from an external device and counts a time based on a clock signal obtained by feeding back an output signal. A subtractor 2 subtracts the numeral of count from reference time information and an adder 3 an error of a clock signal at a preceding time to this time and the subtracted result. A latch 4 stores the sum result as a new error, a D/A converter 5 converts the error into an analog signal and the output after D/A conversion controls an output of the clock signal outputted from a voltage controlled oscillator 6. Since the clock signal output is controlled to take synchronization between the reference time information and the generated clock, the given error voltage is kept constant thereby eliminating jitter. |
