| 摘要 |
<p>An output buffer of a MOS semiconductor integrated circuit includes MOSFETs (Q11 to Q1n; Q21 to Q2n) constituting at least one of a driving and a load circuit, a resistive region (43; 44) connected to the gate electrodes (15-1 to 15-n; 20-1 to 20-n) of the MOSFETs (Q11 to Q1n; Q21 to Q2n), an insulation layer (10) formed on the gate wiring layers (15-1 to 15-n; 20-1 to 20-n) and the resistive regions (43; 44), and a metal wiring layer (23A) for signal input, formed on the insulation layer (10) and connected to the resistive regions (43; 44) via a contact hole (45; 46) formed in the insulation layer (10). The width of the contact hole (45; 46) is set so as to be less than the interval between any adjacent two of the gate wiring layers (15-1 to 15-n; 20-1 to 20-n). The metal wiring layer (23A) to which an input signal is supplied is connected to part of the resistive region (43; 44), so that the gate wiring lengths from the metal wiring layer (23A) to the gate electrodes of the MOSFETs (Q11 to Q1n; Q21 to Q2n) will be set to different values. Thus, an input signal is supplied to the MOSFETs (Q11 to Q1n; Q21 to Q2n) with different delay times to operate the MOSFETs (Q11 to Q1n; Q21 to Q2n) at different timings, causing the variation of an output signal to be gentle.</p> |
