| 摘要 |
A memory device (200) is provided which includes an array (202) of rows and columns of memory cells (201). Row decoder circuitry (206) is provided for selecting a given row of cells (201) for access. Circuitry (208, 209) is included for providing a selected one of a plurality of supply voltages to the row decoder circuitry (206), a first positive voltage provided during an active state of the row decoder circuitry (206) and a second positive voltage provided during an inactive state of the row decoder circuitry (206). |
