发明名称 Low power, process and temperature insensitive FET bias circuit
摘要 A bias circuit for an FET switch in which a pinch-off voltage is generated and sets up a current through a first resistor. The current is reflected through a second resistor to establish a voltage differential across the second resistor which is then imposed across the gate-source terminals of the switch FET when it is desired to turn the switch OFF. The relationship of the turn-off voltage imposed across the switch FET to its pinch-off voltage is determined by the ratio of the resistance values of the two matched resistors, which ratio is independent process and temperature. The switch bias circuit thus offers highly reliable operation and at the same time a greatly reduced power consumption.
申请公布号 US4449067(A) 申请公布日期 1984.05.15
申请号 US19810290432 申请日期 1981.08.06
申请人 PRECISION MONOLITHICS, INC. 发明人 NISHIKAWA, YUKIO
分类号 H03K17/00;H03K17/567;(IPC1-7):H03K17/14;H03K17/68 主分类号 H03K17/00
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