| 摘要 |
To provide an inexpensive test apparatus for testing the performance of control computers in automotive vehicles, for example sufficiently simple to be affordable by gasoline service stations, small garages and the like, a shift register-memory combination unit is provided receiving the data in serial, preferably Pulse-Duration-Modulated (PDM), form, and a monostable flip-flop is connected to the shift register, connected to be SET by a flank, preferably the trailing flank, of the first bit of a data word, and having a timing period somewhat longer than the longest interval between sequential bits, the monostable flip-flop being connected to control the shift register to transfer data in the shift register to a memory section thereof for simultaneous display of the data in the various storage locations of the memory section of the shift register. A counter can be used to inhibit application of clock pulses to the shift register beyond a predetermined count so that only those data which have been transmitted up to the inhibit count will be stored in the shift register for subsequent display.
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