System for synchronizing data frame groups in a serial bit stream.

摘要

A ysnchronizer in a receiver for a serial data stream includes a shift register for temporarily storing the most recently received data. Taps at a plurality of locations on such shift register provide bit signals at regularly spaced locations. A cycle shift register is clocked each time a true frame bit is received. Combinational logic connected to the data taps determines whether a pattern indicating a possible multiframe alignment exists at the data taps. Multiframe candidates are stored in the cycle shift register until all but one are eliminated, with the remaining candidate indicating multiframe alignment.