发明名称 |
Data transfer using bus address lines |
摘要 |
A computer system can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.
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申请公布号 |
US5274784(A) |
申请公布日期 |
1993.12.28 |
申请号 |
US19910791468 |
申请日期 |
1991.11.13 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ARIMILLI, RAVI K.;DHAWAN, SUDHIR;NICHOLSON, JAMES O.;SIEGEL, DAVID W. |
分类号 |
G06F13/28;G06F13/42;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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