| 摘要 |
A memory architecture, suitable for a dynamic random access memory (DRAM) reduces layout area by sharing sense amplifiers, and arranging sense amplifiers to minimize die area. The sense amplifiers, comprising N-sense and P-sense amplifiers, are laid out in a region between memory array portions having memory cells that are each coupled to a digit line in a plurality of alternatingly sequenced digit line pairs. Each region has one N-sense amplifier for every two digit line pairs, and one P-sense amplifier for each digit line pair. Each N-sense amplifier is shared between two memory array portions, and is separated from each by an NFET isolation switch. Each P-sense amplifier is neither shared between the two memory array portions, nor separated from its corresponding memory array portion by an NFET isolation switch.
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