| 摘要 |
A system for sampling an analog or digital data signal at a relatively high rate utilizing relatively slow circuitry. The system includes several sample and hold circuits, each of which receive the data signal. The sample and hold circuits are clocked by respective clock signals that are at the same frequency but equally phased apart from each other. Thus, the sample and hold circuits take samples of the data signal at times that are equally spaced apart from each other. Each of the sample and hold circuits is connected to a series of shift registers that are clocked at the same frequency as the clock used to clock the sample and hold circuit to which they are connected. The shift registers operate to sequentially store samples obtained by their respective sample and hold circuit. The output of the shift registers may be applied to the column drivers of a conventional matrix display.
|
