发明名称 BUFFER MEMORY WRITE CONTROL METHOD AND CONTROL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To maintain a cell data length at a fixed value and to reduce the capacity of a buffer memory by continuing to successively overwrite data that exceeds a fixed number in the leading address of the next cell when long cell data is transferred. SOLUTION: When both a receiving enabling signal 17 and a data transfer signal 18 are active, a write clock 15 is synchronized and data 16 is inputted. In the case of including a long cell data section 1 where the data number of the data 16 is more than a specific value 53, when a producing means of a write address signal 21 detects a header information signal 19 with the signal 17 on an H level and the signal 18 on an L level, the increment of a write address is performed. When a 2nd header information signal is not detected even if the data number exceeds a fixed value, the increment of the write address is suspended, the numeric value of the same address position is continuously outputted, error data of a section 3 are continuously overwritten in the write address and the increment is resumed from the 53 when 2nd header information is detected.
申请公布号 JPH11234346(A) 申请公布日期 1999.08.27
申请号 JP19980035832 申请日期 1998.02.18
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NISHISASHI MASANORI;OHASHI MASAHIRO
分类号 H04L13/08;H04L12/28;H04Q3/00;(IPC1-7):H04L13/08 主分类号 H04L13/08
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