Methods and apparatus for generating multiplicative inverse product

摘要

An multiplier circuit that generates a negate product -B*C quickly without requiring a separate negate operation. This multiplier circuit uses partial product multiplication and any of a variety of multiplication techniques, such as bit-pair recoding or the Booth algorithm, to perform multiplication and negate multiplication operations. The multiplier circuit uses an encoder circuit to produce encoded multiplier strings in accordance with such multiplication techniques. The multiplier circuit reorders bits of such encoded multiplier strings to cause a binary multiplier circuit to generate the negate product -B*C rather than the product B*C. The reordering can be accomplished in any manner, such as by a bus coupling the encoder circuit to the binary multiplier circuit. The encoder circuit can be coupled to the binary multiplier circuit using two buses and a multiplexor circuit. One bus might reorder the bits of the encoded multiplier strings to cause the binary multiplier circuit to produce the negate product -B*C and the other bus might pass the encoded multiplier strings to the binary multiplier circuit without reordering its bits so that the binary multiplier circuit produces the product B*C. The multiplexor may be used to select one of these two buses depending upon which product is desired. This multiplier circuit might be used in a circuit that performs a multiply/add calculation to produce the result A+B*C and that performs a multiply/subtract calculation to produce the result A-B*C.