Charge level maintenance in a memory

摘要

In one embodiment, a memory such as a dynamic random access memory employs charge boosting to bitcells prior to sensing charge levels in the storage nodes of the bitcells. It is believed that such an arrangement may be employed to improve bitcell read-out voltages, reduce refresh power consumption, improve restore voltage levels or other features, depending upon the particular application. Other aspects are described herein.

主权项

1. An apparatus, comprising:
an array of dynamic random access memory (DRAM) cells, each cell having a storage node; and a memory controller coupled to the array of DRAM cells, the memory controller including sense amplifiers configured to sense and restore a charge level in a storage node of a DRAM cell of the array, and a charge level boost circuit configured to add charge to the storage node of the cell to boost the charge level of the storage node of the cell; wherein the memory controller is configured to control the charge level boost circuit to initiate adding charge to the storage node of the cell to boost the charge level of the storage node of the cell prior to sensing a charge level of the storage node of the cell; and wherein the memory controller is configured to control sense amplifiers to sense a boosted charge level stored in the cell after the charge adding has been initiated to add charge to boost the charge level of the storage node, and to restore a charge level in the cell as a function of the sensed boosted charge level.