| 发明名称 | Semiconductor memory device and method of controlling the same | ||
| 摘要 | A plurality of word lines extend in a first direction and are disposed in a second direction and a third direction. A plurality of bit lines extend in the third direction and are disposed in the first direction and the second direction. A global bit line is coupled in common to the plurality of bit lines. A selection elements is disposed between the bit line and the global bit line. A control circuit is able to perform respective operations of reading, writing, and deletion on the storage element. A resistive element is disposed on the global bit line side with respect to the selection element. The resistive element adjusts a magnitude of a voltage to be applied to the selection element according to a magnitude of a current flowing through the selection element. | ||
| 申请公布号 | US9349446(B2) | 申请公布日期 | 2016.05.24 |
| 申请号 | US201514593254 | 申请日期 | 2015.01.09 |
| 申请人 | Kabushiki Kaisha Toshiba | 发明人 | Murooka Kenichi |
| 分类号 | G11C13/00;G11C5/06;G11C5/02 | 主分类号 | G11C13/00 |
| 代理机构 | Oblon, McClelland, Maier & Neustadt, L.L.P | 代理人 | Oblon, McClelland, Maier & Neustadt, L.L.P |
| 主权项 | 1. A semiconductor memory device, comprising: a plurality of word lines that extend in a first direction, the plurality of word lines being disposed in a second direction and a third direction by respective predetermined distances, the second direction intersecting the first direction, the third direction intersecting the first direction and the second direction; a plurality of bit lines that extend in the third direction, the plurality of bit lines being disposed in the first direction and the second direction by respective predetermined distances; a variable resistance layer disposed between the word line and the bit line, the variable resistance layer functioning as a storage element; a global bit line coupled in common to the plurality of bit lines; a selection element disposed between the bit line and the global bit line; a control circuit able to perform respective operations of reading, writing, and deletion on the storage element; and a resistive element disposed on the global bit line side with respect to the selection element, the resistive element having a function to adjust a magnitude of a voltage to be applied to the selection element according to a magnitude of a current flowing through the selection element. | ||
| 地址 | Minato-ku JP | ||