Biasing circuit for level shifter with isolation

摘要

A circuit includes a biasing circuit that includes a load circuit coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the load circuit in response to a transition of the ISO signal between a high voltage and a low voltage. The biasing circuit also includes circuitry to generate an isolation delayed (ISO_DEL) signal. The ISO_DEL signal has a high voltage in response to the biasing signal being within a first threshold level and the ISO_DEL signal has a low voltage in response to the biasing signal being within a second threshold level. The biasing circuit outputs the ISO_DEL signal.

主权项

1. A circuit comprising:
a level shifter; and a biasing circuit coupled to the level shifter, the biasing circuit comprising:
a load circuit coupled to a first node that is coupled to the level shifter, the biasing circuit to output a biasing signal on the first node;a timer component and a current source, wherein an input of the timer component is coupled to receive an isolation (ISO) signal, wherein the current source is configured to inject current for a period of time, as determined by the timer component, into the load circuit in response to a transition of the ISO signal between a high voltage and a low voltage, wherein the high voltage is higher than the low voltage; andcircuitry to generate an isolation delayed (ISO_DEL) signal, wherein the ISO_DEL signal comprises a high voltage in response to the biasing signal being within a first threshold level and wherein the ISO_DEL signal comprises a low voltage in response to the biasing signal being within a second threshold level, the biasing circuit to output the ISO_DEL signal to the level shifter on a second node.