| 发明名称 | Memory architecture | ||
| 摘要 | A first current value flowing through a transistor coupled with a storage node of a memory cell is determined when the transistor is off. A second current value flowing through the transistor is determined when the transistor is in on. A first reference voltage value at a reference node of the memory cell when the transistor is off is higher than a second reference voltage value at the reference node when the transistor is on. Based on the first current value, the second current value, and a relationship between the first current value and the second current value, a number of memory cells to be coupled with a data line associated with the memory cell is determined. | ||
| 申请公布号 | US9443574(B2) | 申请公布日期 | 2016.09.13 |
| 申请号 | US201313793945 | 申请日期 | 2013.03.11 |
| 申请人 | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. | 发明人 | Katoch Atul;O'Connell Cormac Michael |
| 分类号 | G11C11/412;G11C8/08;G11C11/419;G11C29/02;G11C29/12;G11C29/50 | 主分类号 | G11C11/412 |
| 代理机构 | Hauptman Ham, LLP | 代理人 | Hauptman Ham, LLP |
| 主权项 | 1. A method comprising: determining a first current value flowing through a transistor coupled with a storage node of a memory cell when the transistor is off; determining a second current value flowing through the transistor when the transistor is on, wherein a first reference voltage value at a reference node of the memory cell when the transistor is off is higher than a second reference voltage value at the reference node when the transistor is on; and based on the first current value, the second current value, and a relationship between the first current value and the second current value, determining a number of memory cells to be coupled with a data line associated with the memory cell. | ||
| 地址 | TW | ||