发明名称 SYSTEM FOR DATA TRANSFER
摘要 PURPOSE:To transfer data with a small quantity of hardware, by supplying the address of a slave input/output control device, where the access should be started, from a CPU to a master input/output control device. CONSTITUTION:A CPU1000 initializes a mastrer input/output control device IOC 100 for read/write designation, address, and data length. The CPU1000 causes the IOC100 to issue the first bus use request signal to a bus use request signal line A1 to start the IOC100. Next, when conditions satisfy the request due to the bus use request signal, the CPU1000 transmits a bus use permission signal and an IOC designating signal to signal lines B and C respectively. The IOC100 designated by this designating signal outputs initialized read/write designation, address, read or write control signal, and IOC access signal to signal lines F, H, D or E, and G respectively. Thus, data is transferred between the IOC100 and a designated slave IOC200.
申请公布号 JPS57125426(A) 申请公布日期 1982.08.04
申请号 JP19810011218 申请日期 1981.01.28
申请人 NIPPON DENKI KK 发明人 HARA KAZUMI
分类号 G06F13/38;G06F13/362 主分类号 G06F13/38
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