| 摘要 |
PURPOSE:To provide an ultrasonic flaw detector provided with a peak hold circuit capable of executing peak hold processing in high speed. CONSTITUTION:In an ultrasonic flaw detector, a peak hold circuit has comparators 41, 45 and switchers 43, 46 for receiving input data signal, and dual port memories (DPM) 44, 47 for receiving the output from the switchers 43, 46, respectively. Data signals are received at indication periods including a plurality of transmission pulse periods and the maximium value is detected at each sampling interval among the amplitude of signal waveform of the reflection pulse interperiods. |
