发明名称 STEREO DEMODULATING CIRCUIT
摘要 PURPOSE:To obtain a good demodulating signal up to a high band by controlling a loop gain of a PLL circuit by a synchronous detecting output, and making a capture range and a locking range in case of receiving a stereophonic broadcost narrower than those in case of receiving a monaural broadcast. CONSTITUTION:When a PLL circuit 3 is locked to a pilot signal in phase, the pilot signal is detected synchronously by a frequency dividing signal from a 1/2 frequency divider 12 in a phase comparing circuit 13, and it is detected that a stereo is being received, by a stereo-monaural discriminating circuit 14 from a synchronuous detecting output from the circuit 13. As a result, a transistor 16 is turned on, a high level signal is supplied to a connecting switch circuit 21 from an invertor circuit 22, and the circuit 21 is turned on. Also, a series circuit of resistors 20a, 20b operates as a bleeder to a signal from an LPF5, and a cature range and a locking range of the circuit 3 are made narrower than those in case of receiving a monaural broadcast. Accordingly, no distortion is generated in a high band side of demodulating signals of left and right side signals of switching circuits 10L, 10R.
申请公布号 JPS59161143(A) 申请公布日期 1984.09.11
申请号 JP19830035545 申请日期 1983.03.04
申请人 SONY KK 发明人 HASEGAWA MASARU
分类号 H03D1/22;H04H40/45 主分类号 H03D1/22
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