| 摘要 |
PURPOSE:To reduce delay and to shorten an arithmetic time and to speed up processing by setting arithmetic operation for an exponent part corresponding to the overflow of a mantissa part previously by parallel processing and then alternatively selecting thereafter. CONSTITUTION:An adder 11 adds exponent parts ex and ey of input data by performing bias processing and then an adder 12 adds 1 corresponding to the overflow to an output e11; and an adder 13 adds 2 corresponding to two overflows to an output e11 and the results are sent to a selector 14. Then the selector 14 selects one signal among e11-e13 according to signals NORM and RND based upon the arithmetic result of the mantissa part to generate an arithmetic output ep. Consequently, the overflows of the mantissa part caused by normalization and rounding are set previously by the parallel processing and only one of three is merely selected, so the delay is reduced and the arithmetic speed is increased to speed up the operation. |
