| 摘要 |
PURPOSE:To improve the transmission speed by preparing n-sets of PN series whose phases are deviated, making each correspondent to an M-bits of digital data and allowing the receiver side to detect the correlation between a reception signal and the n-sets of PN series generated at the receiver side so as to demodulate the logic. CONSTITUTION:A synchronization control section 16 sends a latch signal SL synchronously with a peak position of a peak P to a latch circuit 13, which latches an output of a comparator 12 at every reception of the latch signal SL and demodulates a signal on lines COR0, COR1, COR2, COR3 respectively to logical '00', '11', '10', '01'. Thus, a peak appearing at each period of the received PN series is detected and to which correlation device the peak appears is discriminated, then the data is demodulated and since not one bit but log2n=M=2 bits is assigned to one PN series, the transmission speed is enhanced in comparison with a conventional system in which '1', '0' are allocated. |
