发明名称 MONITORING CIRCUIT FOR PHASE-LOCKED LOOP CIRCUIT
摘要 PROBLEM TO BE SOLVED: To surely detect the step-out and the abnormality of a voltage controlled oscillator by outputting an alarm signal after detecting the peak of the output signal of a 3rd flip-flop which divides the signal obtained by inverting a reference signal into two signals and also the peak of the output signal of a 4th flip-flop which inputs the inverted output signal of a 2nd flip-flop. SOLUTION: The inverted output signal of a terminal Q of a 2nd flip-flop F2 and an inverted reference signal *Fin are divided into two signals each by a 3rd flip-flop F3 and inputted to a 4th flip-flip F4. The flip-flop F4 outputs an output signal L or H when the synchronization of phase is established or in a step-out state. A peak detection part 7 detects the signal L or H and transmits an alarm signal ALM. When the divided output signal Fout of a voltage controlled oscillator VCO 1 is abnormal, i.e., fixed at an H or L level, the part 7 transmits the signal ALM. Thus, the abnormality of a phase-locked loop circuit is surely detected.
申请公布号 JPH10163863(A) 申请公布日期 1998.06.19
申请号 JP19960321289 申请日期 1996.12.02
申请人 FUJITSU LTD 发明人 ITO ATSUSHI;FUKUTOMI SATOSHI
分类号 H03L7/095 主分类号 H03L7/095
代理机构 代理人
主权项
地址