发明名称 MANUFACTURE OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To improve the processing controllability of a columnar member and planarity of a layer insulation film, when a pillar technique is used in a connection process of a lower wiring and an upper wiring. SOLUTION: A columnar member 15 is formed into a connection region, which electrically connects a lower layer wiring 14 and an upper layer wiring 17 and a specified region excepting a connection region, and a layer insulation film 16 covering the columnar member 15 is formed thereafter. Data of an arrangement position of a columnar member formed in a specified region, excepting a connection region can be obtained by a logical sum negative query processing (NOR processing) of data, for example, corresponding to the arrangement information of an arrangement position of the lower wiring 14 and the arrangement information of the arrangement position of the upper layer wiring 17, based on both the information.
申请公布号 JPH11204635(A) 申请公布日期 1999.07.30
申请号 JP19980005066 申请日期 1998.01.13
申请人 TOSHIBA CORP 发明人 MATSUNOU TADASHI
分类号 H01L23/522;H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L23/522
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