Receiver, programmable circuit and method for computing digital filters

摘要

The circuit comprises a calculation section including an accumulator for accumulating an intermediate result of successive products between the input data and the filter coefficients. An iterative calculation is executed in this way, using an initial anticipated coefficient result for the current value. The control is programmed to forecast the last iteration of the calculation, anticipated by the current result, by the reception of new data. The circuit constitutes a filter of length L for obtaining a sequence of filter results (yn) by multiplication of predetermined coefficients (wk) by input data (xn-k) received at instant (n-k), and p is a positive integer equal to the number of products which can be effected in parallel by the computing unit. Each iteration is carried out as a sum of p products of p successive input data already utilized in the computation of the preceding filter result. The circuit comprises a set of control units cooperating with the computing unit, and a central control unit for constituting a set of multiplexed digital filters. The central control unit comprises a priority instruction in connection with each filter for the start of computing procedure anticipating the filter result as a function of the filter priority. The control unit is implemented as an automaton with four states, namely for (a) an initialization for memory storage of each filter coefficients; (b) an inactivation for waiting for the arrival of new input datum; (c) the iterative computing procedure with accumulation of intermediate result; and (d) the computing of latest interaction. Independent claims are included for a television receiver for digital television which comprises a demodulator block containing the proposed filter circuit, and a filter calculation method.