| 摘要 |
PURPOSE:To provide a bus collation type processor for realizing failsafe collation by using normal non-failsafe collation logic without using special failsafe collation logic in a bus collation logic circuit. CONSTITUTION:This processor is constituted of a timer for activating an intermittent diagnostic processing, two duplex processors 11a and 11b activated by the timer for supplying test data strings including non-coincident data onto a bus and a diagnosis control circuit 18 for monitoring the response of the bus collation logic circuit 12 to the test data and outputting judgement output inverted for respective intermittent diagnostic processing cycles when the response indicates an operation stipulated beforehand. Thus, the degradation of processing performance which is a fault in the case of turning the bus collation logic circuit to failsafe is prevented, collation logic is simplified, the processor is miniaturized by the simplification and reliability is improved. |
