Semiconductor devices and methods of manufacturing the same

摘要

Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The methods may include forming a sacrificial gate pattern on a substrate, forming a first spacer on a sidewall of the sacrificial gate pattern and forming a first interlayer dielectric (ILD) layer covering a sidewall of the first spacer and exposing a top surface of the first spacer. The first spacer may expose an upper portion of the sidewall of the sacrificial gate pattern. The methods may also include forming a capping insulating pattern covering top surfaces of the first spacer and the first ILD layer, replacing the sacrificial gate pattern with a gate electrode structure and patterning the capping insulating pattern to form a second spacer on the first spacer and between the gate electrode structure and the first ILD layer. The second spacer may be formed of a material having a dielectric constant higher than a dielectric constant of the first spacer.

主权项

1. A method of manufacturing a semiconductor device, comprising:
forming a sacrificial gate pattern on a substrate; forming a first spacer on a sidewall of the sacrificial gate pattern, the first spacer exposing an upper portion of the sidewall of the sacrificial gate pattern; forming a first interlayer dielectric (ILD) layer covering a sidewall of the first spacer and exposing a top surface of the first spacer, the first ILD layer having a top surface that is lower than a top surface of the sacrificial gate pattern and is higher than the top surface of the first spacer; forming a capping insulating pattern covering the top surfaces of the first spacer and the first ILD layer; replacing the sacrificial gate pattern with a gate electrode structure; and patterning the capping insulating pattern to form a second spacer on the first spacer and between the gate electrode structure and the first ILD layer, wherein the second spacer is formed of a material having a dielectric constant higher than a dielectric constant of the first spacer, wherein forming the capping insulating pattern comprises: forming a capping insulating layer conformally covering the top surfaces of the sacrificial gate pattern, the first ILD layer, and the first spacer; and performing a planarization process on the capping insulating layer to expose the top surface of the sacrificial gate pattern, wherein the capping insulating layer comprises a first portion disposed on the sacrificial gate pattern and a second portion disposed on the first ILD layer, the method further comprises forming a protection insulating pattern on the second portion of the capping insulating layer, wherein the protection insulating pattern protects the capping insulating layer during the planarization process.