发明名称 PLL CIRCUIT
摘要 PURPOSE:To secure the output frequency over a wide range by adding the divider circuit to divide the output of the voltage control oscillator and the switch circuit to select the oscillation output or the division output in accordance with the output of the low pass filter at the front step of the oscillator to the PLL circuit. CONSTITUTION:The output of phase comparator 1 is changed to DC through low pass filter 2, and voltage control oscillator 3 is actuated according to the DC output voltage or the DC output voltage obtained by amplifying the first DC output voltage. Oscillation frequency fv obtained through oscillator 3 is used as output frequency fo of this system, and at the same time output frequency fo/N of divider 4 which is capable of program with optional integer N is compared with input reference frequency fR through comparator 1. In such constitution, divider 21 which features division number M1 and divides frequency fv and divider 22 of division number M2 are provided in series, and these output frequency fv/M1 and fv M2 are selected through selection switch circuit 23 to be applied to divider 4. Switch 24 of circuit 23 is controlled by output DC voltage Vin of filter 2.
申请公布号 JPS5464956(A) 申请公布日期 1979.05.25
申请号 JP19770131783 申请日期 1977.11.02
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 TAKADA SHIGEO
分类号 H03L7/18;H03L7/183 主分类号 H03L7/18
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