Dual plane well-type two-phase ccd

摘要

A charge coupled device having geometries suitable for fabrication in high density packages (64,000 bits per chip-1,000,000 bits per chip) is comprised of a semiconductor substrate having dopant impurity atoms of a first type and a first surface. A charge transfer channel lies in the substrate near the first surface, and it is overlaid by an insulating layer of non-uniform thickness. A plurality of first and second electrodes lie on the insulating layer traversely to the channel. A well region of dopant impurity atoms of a second type opposite to the first type lies under each of the electrodes. The non-uniform insulating layer underlies each of the first electrodes by a first uniform thickness, underlies the second electrodes by a second uniform thickness, and separates the each of the first and second electrodes by approximately the second thickness. The second thickness is 20%-60% greater than the first thickness to greatly reduce inter-electrode shorts in high density packages. A shallow layer of dopant impurity atoms of the second type may be provided under the second electrodes to compensate for shift flatband voltage shifts due to the thick insulating layer.