发明名称 |
Parallel-serial converter |
摘要 |
A parallel-serial converter comprises a plurality of selection-delay unit circuits. The unit circuit selectively receives an output signal from the immediately preceding unit circuit and one of a plurality of input parallel signals and shifts the selectively received signal to the immediately succeeding unit circuit. The selection-delay unit circuit is only formed of three transfer gates and two inverters in order to reduce a chip size and save power consumption.
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申请公布号 |
US4418418(A) |
申请公布日期 |
1983.11.29 |
申请号 |
US19810324557 |
申请日期 |
1981.11.24 |
申请人 |
TOKYO SHIBAURA DENKI KABUSHIKI KAISHA |
发明人 |
AOKI, KAZUHIDE |
分类号 |
G11C19/28;G11C19/38;H03M9/00;(IPC1-7):G11C19/28;H03K23/22 |
主分类号 |
G11C19/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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