| 摘要 |
<p>PURPOSE:To realize size reduction, high accuracy, wide-range adjustment of pulse width, general usefulness, and simple adjustment by integration, by composing a clock extracting circuit of 1st and 2nd differentiation circuits, and 1st and 2nd monostable multivibrators. CONSTITUTION:When a pulsating input signal Sin is supplied to an input terminal 1, a signal Sin is delayed by a delay gate 11 in the 1st differentiation circuit 10 into a delay signal S11, which is differentiated by an AND gate 12 at the trailing edge of the signal Sin to set the 1st monostable multivibrator 20 at its pulse 12. Consequently, the 1st monostable multivibrator 20 outputs a signal S20 with pulse width t1. The signal S20 is delayed by a delay gate 31 in the 2nd differentiation circuit 30 into a delay signal S31, which is differentiated by an AND gate 32 at the trailing edge of the signal S20 to set the 2nd monostable multivibrator 40 with its pulse S32. Then a signal S40 with pulse width t2 is outputted. The phase of the S32 can be adjusted freely by varying an external variable resistance 60. Further, the pulse width t2 of the signal 40 is freely adjusted independently of the signal 20 by varying an external variable resistance 70.</p> |
