| 摘要 |
In a digital data processor having a CPU, a condition instruction is fetched from memory to an instruction register. A first control circuit responds to source-codes to select the general registers having respective pieces of data to be compared. A first latch stores instruction data including a code for an operation to be performed by an arithmetic and logic unit (ALU) on the two pieces of data under the control of a second control circuit. A conditional code register stores a conditional code. representing the result of the ALU operation, and a second latch stores selection criteria for destination registers specified by the instruction. A selection circuit operates under the control of a third control circuit to sort the ALU output data of a third control circuit to the specific destination register in accordance with the selection criteria and the condition code. The instruction execution is completed within a single CPU cycle.
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