MULTIPLE CHANNEL DELAY CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT TESTING DEVICE USING THE SAME

摘要

PROBLEM TO BE SOLVED: To output the delay clock signals of multiple channels by a delay element. SOLUTION: By the output signal 2-1 that a clock signal is delayed by 3ns by a delay element 2, an address generator 7 generates an address '0', select data '1ns' is imparted from a memory 6 to a selector 5, the output signal 5-1 of delay time 1ns which is obtained from the delay element 2 and the control signal 4-2 outputted from a controller 4 are added to an AND gate 8-2 and the clock signal delayed by 1ns is outputted. Next, the address generator 7 generates an address '1' by the output signal 2-1 delayed by 3ns by the delay element 2, selector data '2ns' is imparted from the memory 6 to the selector 5, the output signal 5-1 of delay time 2ns which is obtained from the delay element 2 and the output signal 14-3 of the controller 4 are added to an AND gate 8-3 and a clock signal delayed by 5ns is obtained.