| 摘要 |
<p>PURPOSE:To shorten the establishment time of phase locked loop and stabilize synchronism holding by comparing the detection timing of the 2nd synchronous signal in an input signal with the timing of the 2nd regenerated phase locked loop signal and detecting the step out of a regenerated clock, and resetting a frequency dividing circuit and performing leading-in operation forcibly. CONSTITUTION:For example, an input signal is normal and a dropout signal DO' indicating its abnormality is at a low level. When a counter 131 counts up eight times continuously with a window pulse IFPW, a signal C goes up to a high level and the counter stops operating. Simultaneously, an AND circuit 141 enters a passing state to supply a frame pulse signal FP to a latch 142, whose latch output resets a loop filter 6 and frequency dividing circuits 11 and 12 to specific initial states. Synchronism is obtained a specific time later and a synchronism holding state is entered. In the synchronism holding state, the signal FP is within the window pulse IFPW, so the counter 13 is cleared at every signal PF and not reset, holding the synchronism stably.</p> |
