发明名称 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS
摘要 A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.
申请公布号 US2007204075(A1) 申请公布日期 2007.08.30
申请号 US20070672921 申请日期 2007.02.08
申请人 发明人 RAJAN SURESH N.;SCHAKEL KEITH R.;SMITH MICHAEL J.S.;WANG DAVID T.;WEBER FREDERICK D.
分类号 G06F13/28 主分类号 G06F13/28
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