| 摘要 |
A method for planarizing a semiconductor device is provided to prevent the generation of humps at cell and peripheral regions and to prevent the malfunction of the semiconductor device by preventing the damage of a self-aligned contact nitride layer using the self-aligned contact nitride layer of a bottom portion of an interlayer dielectric as a planarization stop layer. A plurality of gate lines are formed on a substrate. A spacer insulating layer(39) is formed on the entire surface of the resultant structure. A self-aligned contact nitride layer(40) is deposited on the spacer insulating layer. An interlayer dielectric(41) is deposited on the self-aligned contact nitride layer. The interlayer dielectric is planarized by using the self-aligned contact nitride layer as a planarization stop layer, so that the self-aligned contact nitride layer is protected from the planarization.
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