DIGITAL DATA RETIMING DEVICE IN HIGH-SPEED DATA TRANSMISSION

摘要

The device has a local clock pulse generator (11) to generate a local clock pulse (FT). The local clock pulse generated has a frequency that is six times the bit rate of the input binary D. The external input clock pulse (CP) is delayed sequentially at intervals of one period of the local clock pulse by the clock pulse parallel generator (12). Given delayed clock pulses (CP1-CP7) are generated. An input data transition detector(13) detects the transition of the input data and outputs the pulse (DT) with a width larger than the width of the minimum permissible clock pulse of the flip flop that belongs to each constructed. A sequential logic parallel phase detector (14) provides a clock pulse selection information by comparing the delayed clock the pulse signal (CP) from the clock pulse parallel generator and the pulse (DT) from the input data transition detector. A retiming clock pulse selector (15) outputs a retiming clock pulse based on the selection information. A time delay compensation unit (16) performs the compensation delay of the input data based on the retiming clock pulse. A data retiming unit (17) performs the retiming of the delay data (DD) output by time delay compensation unit and outputs data (DR).