| 摘要 |
a transmitting unit for receiving a system clock and a reset signal to provide four-divided clock of the system clock to a receiving part, for inputting a self cell starting signal and a 8-bit unit of self cell input data to be synchronous to a self cell clock, for receiving an alternate cell starting signal and 32-bit unit of alternate cell input data, for checking whether the input data is transmitted to any of first and second rings and transmitting a transmitting data starting signal and the 32 bit unit of transmitting data and transmitting data writing signal to the checked ring; and a receiving unit for receiving the system clock, the reset signal and the four-divided clock from the transmitting unit, for providing an alternate cell write signal, an alternate cell starting signal synchronous to the four-divided clock and 32-bit unit of alternate cell input data to the transmitting unit, for reading the received data synchronous to the four-divided clock to check the destination place of the read data, and if the destination place is the same as a module acknowledge number, for extracting 8-bit unit of extracting data, but if different, for transmitting the 32-bit unit of alternate cell input data to the transmitting unit |
