发明名称 Memory device
摘要 According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.
申请公布号 US9368160(B2) 申请公布日期 2016.06.14
申请号 US201414472094 申请日期 2014.08.28
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 Murooka Kenichi
分类号 G11C5/06;G11C5/02;G11C13/00;G11C7/10 主分类号 G11C5/06
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A memory device comprising: a plurality of global bit lines extending along a first direction; a pair of word lines separated from each other, extending along a second direction; a first bit line between the pair of word lines, extending along a third direction different from the first direction and the second direction; first variable resistivity layers between the first bit line and each word line of the pair of word lines; and a first selector between the first bit line and one of the plurality of global bit lines, wherein the first selector includes: a first semiconductor layer coupled with the first bit line and the one of the plurality of global bit lines, anda pair of gates on two side surfaces of the first semiconductor layer facing each other in the first direction with first gate insulating layers therebetween.
地址 Minato-ku JP