发明名称 Semiconductor device
摘要 A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.
申请公布号 US9377825(B2) 申请公布日期 2016.06.28
申请号 US201414296552 申请日期 2014.06.05
申请人 RENESAS ELECTRONICS CORPORATION 发明人 Shinohara Minoru;Araki Makoto;Sugiyama Michiaki
分类号 H01L23/50;G06F1/18;G11C5/02;G11C5/06;H01L23/538;H01L25/065;H01L25/18;H01L23/00 主分类号 H01L23/50
代理机构 Shapiro, Gabor and Rosenberger, PLLC 代理人 Shapiro, Gabor and Rosenberger, PLLC
主权项 1. A semiconductor device comprising: a wiring board having a main surface, a rear surface opposite to the main surface, a long side, a short side intersecting the long side, a plurality of first terminals arrayed along the long side on the main surface, a plurality of second terminals arrayed along the short side on the main surface, and external connecting terminals formed on the rear surface; a memory chip mounted over the main surface of the wiring board, the memory chip having a first main surface, a first side, a second side intersecting the first side, and a plurality of first electrodes arrayed along the second side on the first main surface, the first electrodes being connected with the second terminals of the wiring board via a plurality of first wires; and a controller chip mounted over the first main surface of the memory chip, the controller chip being operable to control the memory chip and having a second main surface and a plurality of second electrodes arrayed on the second main surface, the second electrodes being connected with the first terminals of the wiring board via a plurality of second wires, wherein the long side of the wiring board includes a first portion and a second portion, and the first terminals are arrayed between the first side of the memory chip and the first portion of the long side of the wiring board in a plan view, wherein a distance between the first portion of the long side of the wiring board and the first side of memory chip is greater than a distance between the second portion of the long side of the wiring board and the first side of the memory chip in a first direction perpendicular to the first side of the memory chip, and wherein the second terminals are arranged on a first area of the main surface of the wiring board between the second side of memory chip and the short side of the wiring board.
地址 Tokyo JP