Parallel bitline nonvolatile memory employing channel-based processing technology

摘要

Various aspects provide for a new combination of non-volatile memory architecture and memory processing technology. A memory cell has a gate node, a source node and a drain node. The gate node is connected to a wordline of the memory, the source node is connected to a local source line of the memory, and the drain node is connected to a local data line of the memory. A channel-based processing component programs the memory cell and inhibits programming of a second memory cell on the wordline of the memory. The channel-based processing component also grounds the local source line and the local data line in conjunction with programming the memory cell, and floats a second local source line and a second local data line connected to the second memory cell in conjunction with inhibiting programming of the second memory cell.

主权项

1. A memory, comprising:
a memory cell having a gate node, a source node and a drain node, wherein the gate node is connected to a wordline of the memory, the source node is connected to a local source line of the memory, and the drain node is connected to a local data line of the memory; and a channel-based processing component configured to program the memory cell and inhibit programming of a second memory cell on the wordline of the memory, the channel-based processing component configured to ground the local source line and the local data line in conjunction with programming the memory cell, and configured to float a second local source line and a second local data line connected to the second memory cell in conjunction with inhibiting programming of the second memory cell.