Memory circuit and cache circuit configuration

摘要

A cache memory die includes a substrate, a predetermined number of sets of memory cells on the substrate, a first set of input/output terminals on a first surface of the cache memory die, and a second set of input/output terminals on a second surface of the cache memory die. The first set of input/output terminals are connected to a primary memory circuit outside the cache memory die. A portion of the second set of input/output terminals are compatible with the first set of input/output terminals.

主权项

1. A memory circuit comprising:
a first memory circuit formed of a first die or a set of stacked dies, the first memory circuit comprising P sets of memory cells of a first type, each set of the memory cells of the first type having Q input/output (I/O) terminals, P and Q being integers greater than 1; a second memory circuit formed of a second die, the second memory circuit comprising D set(s) of memory cells of a second type disposed towards a periphery of the second die, the memory cells of the second type being readable at a speed faster than the memory cells of the first type, and each set of the memory cells of the second type comprising P subsets of Q*N memory cells of the second type, each of the P subsets of memory cells of the second type associated with a corresponding one of the P sets of memory cells of the first type, D and N being positive integers, the first die or the set of stacked dies being stacked over the second die wherein the second die further includes a first plurality of I/O terminals and a second plurality of I/O terminals within a central portion of the second die that is disposed between the sets of memory cells of the second type, the first plurality of I/O terminals being electrically coupled to the first memory circuit by through-silicon vias, and the second plurality of I/O terminals being electrically isolated from the first memory circuit and disposed such that at least one terminal of the second plurality of I/O terminals is between each terminal of the first plurality of I/O terminals and the sets of memory cells; a memory controller circuit electrically coupled with the first memory circuit through the through-silicon vias in the second die, the memory controller circuit being configured to access the P sets of memory cells of the first type; and a cache controller circuit electrically coupled with the memory controller circuit and the second memory circuit, the cache controller circuit being configured to receive a read command for reading requested data stored in the first memory circuit at a read address and to retrieve a valid duplication of the requested data from the second memory circuit if the valid duplication of the requested data exists in the second memory circuit.