| 摘要 |
An integrated circuit logic gate suitable for use in LSI arrays provides OR and NOR logic outputs and includes additional collector and emitter resistors causing the array to be operated at half power levels. If a full power array is desired optional metalization shunting of the additional emitter and collector resistors is provided while maintaining the full logic swing across the same DC reference level which exists for half power operation. Thus, full power and half power gates may be interconnected without necessitating the use of additional interface circuits.
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