| 摘要 |
<p>PURPOSE:To attain reading of data at the same speed from both X and Y directions by actuating X and Y sense means interlocking X and Y line driving means selected by the address signal and transmitting both high and low logic levels of a memory cell. CONSTITUTION:A memory cell array 1 of (mXn) bits has Q corresponding to each bit. The drain terminal of each Q is connected to a high potential VCC. Then the gate and source terminals are connected to the X and Y lines respectively via a wiring means 11 in response to level ''1'' and the data expected to each bit. While the gate and source terminals are connected to the y and X lines respectively via a wiring means 12 in response to level ''0''. The X and Y lines are reset to ''0'' for each input of the signal impressed to an address decoder and the X and Y selection signals respectively in a readout mode. Then an X line driver 2a and a Y line sense amplifier 3b or a Y line driver 2b and an X line sense amplifier 3a are actuated in response to both X and Y selection signals. Thus each Q output is transmitted through a selection part.</p> |
