| 摘要 |
PURPOSE:To reduce relatively a load parasitic to a signal line to be driven by connecting the 1st transfer gate circuits which are connected individually to input terminals to plural signal lines respectively, and connecting the signal lines to an output terminal individually in common through the 2nd transfer gate circuits. CONSTITUTION:When the 1st specific transfer gate circuits TMG1 - TMG64 are switched on, the 2nd transfer gate circuits TMGa - TMGd which share specific signal lines SLa - SLd are switched on together with the 1st transfer gate circuits, and a specific signal is selected among plural input signals and outputted. Consequently, only some of the transfer gate circuits constitute the load parasitic to a signal line to be driven through the 1st transfer gate circuits and the parasitic load is reduced as compared with the total number of the transfer gate circuits.
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