SEMICONDUCTOR MEMORY DEVICE

摘要

The semiconductor memory device is connected to a power source and includes a reference potential line connected to receive a reference potential from the power source. An input circuit (21,Q1,Q2) is connected to the reference potential line and receives an external input signal having a logic level defined in reference to the reference potential to be supplied to the source potential line. The output circuit has an external output terminal which is connected to the reerence potential line. The output circuit is for generating an output to the external output terminal. An inhibiting circuit (Q3) inhibits a response to the exteral input signal of the input circuit for a predtermined period during which the output of the output circuit changes.